                              Release Notes
                              =============

                           Broadcom Bootcode Firmware
                                    For
                                  BCM5720

                 Copyright (c) 2010-2021 Broadcom Corporation
                          All rights reserved.

-------------------------------
Version 1.43 - December 8, 2023
-------------------------------

   Fixes:
   ======
   1.  Problem: DCSG01612601
       NX1 WoL fails to wake up sometimes when in 1G speed

       Cause:
       In Vaux state (S3-S4), with WoL enabled, the clock available
       for 5720 may be too slow to sample the WoL event properly
       in 1G speed.

       Fix:
       Switch to 125MHz PLL clock in S3-S4 state when WoL is
       enabled with 1G speed. Set bit_26(TLP Clock Source) of
       GPHY control status register.

-------------------------------
Version 1.42 - March 17, 2021
-------------------------------

   Fixes:
   ======
   1.  Problem: CTRL-53171
       nx1 sysops test failure observed

       Cause:
       As we are clearing bit_9(CLK_POWER_MGMT) of link_capability
       register, we are observing this issue.

       Fix:
       Do not clear bit_9(CLK_POWER_MGMT) of link_capability
       register.

-------------------------------
Version 1.41 - March 19, 2020
-------------------------------

  Enhancement:
  ============
         1. CTRL-47255: Add OEM support for FoD option.

-------------------------------
Version 1.40 - August 28, 2018
-------------------------------

   Fixes:
   ======
   1.  Problem: CTRL-31193
       LinkCapability should be consistent with LinkStatus.

       Cause:
       Linkwidth in LinkCapability is x2 whereas in LinkStatus
       it is x1 which is causing training error.

       Fix:
       Forced Linkwidth in LinkCapability to x1 to make consistent
       with Linkwidth in LinkStatus.

-------------------------------
Version 1.39 - June 5, 2015
-------------------------------

   Fixes:
   ======
   1.  Problem: CASE#923947
       The SPI clock (i.e. SCLK) runs twice speed
       faster than the default on some OEM platforms.

       Cause:
       The function, which handles the VPD event, 
       accidentally clears the register offset 0x7014 
       Bit [7] that changes SPI_CLK_DIV.

       Fix:
       Fixed the function in question and resolved the issue.
                                
-------------------------------
Version 1.38 - April 13, 2015   
-------------------------------

   Enhancement:
   ============		                         
   1. (JIRA) (CTRL-20347) Add nvram configuration bits to select
      SGMII Mode and 1000base-x.

-------------------------------
Version 1.37 - April 8, 2015   
-------------------------------

   Enhancement:
   ============		                         
   1. (JIRA) (CTRL-20518) 909424: Bootcode version update.

-------------------------------
Version 1.36 - November 19, 2014   
-------------------------------

   Fixes:
   ======
   1. Problem: CQ74011
      Share memory offsets overwritten due to a change in a 
      common header file between bootcode and PM Offload firmware.

      Cause:
      Changes made to this common header intended for PM offload 
      firmware inadvertently overwrites certain offset in share 
      memory for bootcodes compiled with this header file.
     
      Fix:
      fix affected header file and re-release all affected bootcodes.
    
-------------------------------
Version 1.35 - October 21, 2014   
-------------------------------

   Enhancement:
   ============		                         
   1. CQ73784.  NX1 NVRAM L0s & L1s NVRAM entries to match NX2 designs.
      Two NVRAM bits are defined to control ASPM support.

-------------------------------
Version 1.34 - March 5, 2014   
-------------------------------
   Fixes:
   ======
   1. Problem:
      BC v1.33 unexpectedly extends the detection pulse from 500 ns to 4 us.
     
      Fix:
      Bootcode reset the detection pulse to 500 ns.

   Enhancement:
   ============
   1. CQ72062: OEM specific enhancement request to address PCIe link 
      training issue due to improper receiver termination at the link 
      partner.
						  
------------------------------
Version 1.33 - October 10, 2013
------------------------------    
   Enhancement:
   ============		
   1. CQ71212: Adding a NVRAM Control bit (offset 0x21C[1]) to enable/disable 
      AutoNeg 1G half duplex advertisement.
			
-----------------------------
Version 1.32 - March 26, 2013
-----------------------------    
   Enhancement:
   ============		
   1. CQ67974 - Add NVM-CFG option to disable *L1 re-entry* while in D3H.
      A new NVM-CFG bit has been defined at offset 0x21C[0] to disable
      *L1 re-entry*. NVRAM offset 0x21C will be copied to shared memory
      offset 0xe0C.
							  
-------------------------------
Version 1.31 - January 23, 2013
-------------------------------    
   Fixes:
   ======
   1. Problem: CQ67387
      PCIe Gen2 (-3.5dB) Tx Template failure

      Cause:
      The default PCIe Gen2 Transmitter amplitude is not preserved. Bootcode
      overwrites the PCIe Gen2 Transmitter amplitude when programming PCIe Tx
      De-Emphasis.
     
      Fix:
      Bootcode will preserve the PCIe Gen2 Transmitter amplitude to resolve
      this issue.

   2. Problem: CQ67388
      PCIe Tx De-Emphasis for Gen2

      Cause:
      In b57diag secfg #68 configuration controls the PCIe Tx De-Empahsis for
      both Gen1 and Gen2. It's suggested to differentiate this option between
      Gen1 and Gen2 for better clarification.
     
      Fix:
      Using the existing defined control bits to control the PCIe Tx
      De-Empahsis for Gen1. Defined two more control bits in NVRAM to control
      the PCIe Tx De-Empahsis for Gen2. The default setting is -3.5dB for Gen1
      and -6 dB for Gen2.
  
   Enhancement:
   ============		                         
   1. Enabled CPMU power saving modes in Phase 2 instead of Phase 1 to reduce
      Bootcode loading time.
   2. Preserve the configuration data in shared memory in Phase 2 Bootcode
      since Bootcode can no longer be able to read these data after driver
      enabled Interesting packet WOL (0x400[19] = 1).

----------------------------
Version 1.30 - June 20, 2012
----------------------------    
   Enhancement:
   ============		
   1. Add TPH feature support.
      Defined to NVRAM control bits to control TPH feature.
       00: Disable 
       01: Advertise TPH without ST Mode
       10: Advertise TPH with ST Mode 
       
   2. Copy the 4 part ID from Reg 0x6434 and Reg 0x6438 to APE shared memory
      rxCPU write segment area.
                                                             
---------------------------
Version 1.29 - June 1, 2012
---------------------------    
   Fixes:
   ======
   1. Problem: CQ63580
       BC1.28 caused tg3 driver show link detected "no" 
	  
      Cause:
      BAR4 is used for MSIX table and is disabled in Bootcode v1.28, which
      causes tg3 driver to show incorrect link status.

      Change:
      Bootcode will not disable BAR4 to resolve this issue.
                                                                           
---------------------------
Version 1.28 - May 30, 2012
---------------------------    
   Fixes:
   ======
   1. Problem: CQ63121
      Third BAR is Writeable, Causes OS to Assign Memory 
	  
      Cause:
      BAR4 (offset 0x20) is writeable and causes the BIOS/OS to assign a
      memory address for use, even though BAR4 is not used on 5720.  

      Change:
      Bootcode disable BAR4 to prevent write access.
      
   Enhancement:
   ============		
   1. Add 800usec delay before accessing NVRAM (hw workaround) in driver
      absent case and Fast Boot is enabled.
   
   2. Optimizing the NVRAM loading in Phase 1 Bootcode.  All NVRAM access for
      Phase 1 Bootcode will happen in the beginning of the execution.  There
      will be no NVRAM access in Phase 2 Bootcode.  Bootcode will not copy
      PCI IDs to APE shared memory.
                                                 
-----------------------------
Version 1.27 - April 27, 2012
-----------------------------

   Enhancement:
   ============		
   1. CQ 62895. Adding two NVRAM control bits per port for SGMII verification.
      One bit is for enabling SGMII Mode. The other bit is used to select
      force link or autonegotiation.


-----------------------------
Version 1.26 - April 24, 2012
-----------------------------

   Fixes:
   ======
   1. Problem: CQ62817
      NVRAM secfg #68 PCIe Tx De-Emphasis option does not take effect.
	  
      Cause:
      NVRAM secfg #68 PCIe Tx De-Emphasis option does not support PCIe Gen2.

      Change:
      Added PCIe Gen2 Tx De-Emphasis support.
                               
-----------------------------
Version 1.25 - March 22, 2012 
-----------------------------    

   Fixes:
   ======
   1. Problem:  CQ 62273
      Enable and disable LOM repeatedly by toggling Low Power Mode Pin in
      chassis, system will observe RSOD

      Change:
      Change the APE Clock Policy from 125Mhz to 62.5MHz to allow APE Firmware
      to execute upon resuming from Low Power Mode.

-----------------------------
Version 1.24 - March 07, 2012 
-----------------------------    

   Enhancement:
   ============		
   1. Bootcode will copy func_mode information to RxCPU and APE Shared Memory
   for drivers and APE FW after the device is out from reset and when Vmain is
   present.
                                 
-----------------------------
Version 1.23 - March 05, 2012 
-----------------------------    

   Enhancement:
   ============		
   1. Bootcode copy func_mode information to RxCPU and APE Shared Memory for
      drivers and APE FW after the device is out from reset.  Bootcode will
      poll pcie register 0x408 bit 7 for first config done to determine
      whether the device is out from reset.
      
--------------------------------
Version 1.22 - February 16, 2012 
--------------------------------                 

   Enhancements:
   =============
   1.  Change the Bootcode to setup both MSIX table offset and PBA table
       offset to page aligned.
   
-------------------------------
Version 1.21 - January 30, 2012 
-------------------------------

   Enhancements:
   =============
   1. Enabling the ECO that bring down the 5720 Power Consumption in Serdes
      IDDQ Mode by setting 367c[5] to 1.
	  
-------------------------------
Version 1.20 - January 03, 2012 
-------------------------------

   Fixes:
   ======
   1. Problem: 
      The LED remains on after DOS ungraceful shutdown when WOL is disabled. 
	  
      Cause:
      The root cause is that Bootcode cannot successfully power down the
      unused GPHY. Bootcode powered down unused GPHY by read/modify/write mii
      reg 0x00 to set GMII_CONTROL_ISOLATE bit and GMII_CONTROL_POWER_DOWN
      bit. When Bootcode writes back to mii reg 0x0, the
      MII_CONTROL_AUTONEG_ENA bit is still set which keeps the GPHY LED remain
      on.

      Change:
      Modified Bootcode not to read/modify/write when updating mii reg 0x00.
      Bootcode will only write GMII_CONTROL_ISOLATE bit and
      GMII_CONTROL_POWER_DOWN bit to mii reg 0x00 to completely power down the
      unused GPHY.
	  
--------------------------------
Version 1.19 - November 15, 2011 
--------------------------------

   Enhancements:
   =============
   1. Provide the access to Network SerDes adjustment parameter.
      Defined 4 control bits to adjust Network SerDes TX Amplitude and
      Pre-emphasis. Set the default NVRAM settings for the Network SerDes
      TX Amplitude and Pre-emphasis to be closer to the HW default as
      possible. The fiber mode output voltage measurements are closest to the 
      HW default when the TxAmpl/TxPre configuration is 01/00. This common
      default applies to both fiber and SGMII modes.
	  
--------------------------------
Version 1.18 - November 03, 2011 
--------------------------------

   Enhancements:
   =============
   1. Removed V1.15 changes per LSI team request.
      Bootcode set BIT 12 and BIT 11 of Reg 0x40C to 11b in LINK/ACTIVITY LED
      Mode and SPEED10/100 LED Mode.
   
---------------------------------
Version 1.17 - September 21, 2011 
---------------------------------

   Fixes:
   ======
   1. Problem: 
      Get version ID command in NCSI FW does not return correct IDs. 

      Cause:
      Bootcode copy the svid and ssid to the APE shared memory. The get
      version ID command in NCSI FW will read the IDs from here. Each port has
      its own svid and ssid stored in the NVRAM and each port has its own
      space in APE shared memory to store these IDs. However BC only copy the
      svid and ssid of port 0 from NVRAM offset to the APE shared memory for
      all ports.
      
      Change:
      Bootcode will copy the port svid and ssid to its own space of the APE
      shared memory.
	  
------------------------------
Version 1.16 - August 31, 2011 
------------------------------

   Enhancements:
   =============
   1. Removed CQ58029 implementation.
   
------------------------------
Version 1.15 - August 26, 2011 
------------------------------

   Fixes:
   ======
   1. Problem: 
      Bootcode set BIT 12 and BIT 11 of Reg 0x40C to 1 in LINK/ACTIVITY LED
      Mode and SPEED10/100 LED Mode.

      Change:
      Follow the Register Spec to set BIT 12 and BIT 11 to 0 in both modes.
						  
------------------------------
Version 1.14 - August 22, 2011 
------------------------------
   Enhancements:
   =============
   1.CQ58029:  Prevent Entry into PCIe compliance mode.

------------------------------
Version 1.13 - August 11, 2011 
------------------------------
   Enhancement:
   ============	
   1. Trimming the GPHY Hybrid to provide more margin for the Differential
      Output Voltage in 100Mb mode. This is based on the DVT result of the
      5720 across temperature, voltage, and process.

----------------------------
Version 1.12 - July 22, 2011 
----------------------------

   Fixes:
   ======
   1. Problem: 
      In Func_mode support, BC may run into a infinite loop when detecting
      whether the device has come out from reset if the device states in
      reset.

      Change:
      Modify Bootcode to poll for a finite number of times to avoid a dead
      lock situation.
	  
----------------------------
Version 1.11 - July 12, 2011   
----------------------------
   Enhancement:
   ============		
   1. Bootcode copy func_mode information to RxCPU and APE Shared Memory for
      drivers and APE FW.  A signature (0x362c) has been introduced for the
      func_mode information validation.  Driver and APE FW should validate the
      func_mode information in the shared memory by checking this signature.
	  
----------------------------
Version 1.10 - July 06, 2011   
----------------------------
   Enhancement:
   ============		
   1. Bootcode copy func_mode information to RxCPU and APE Shared Memory for
      drivers and APE FW.
	  						  
----------------------------
Version 1.09 - June 20, 2011   
----------------------------
   Enhancement:
   ============
   1. Modified OS absent mode EEE script to improve the link stability.  	  
 
   2. Modified Bootcode to continue monitoring the link status after entering
      Vaux only mode.
   
---------------------------
Version 1.08 - May 10, 2011   
---------------------------

   Enhancement:
   ============
   1. Update OS absent mode EEE script.  
      The OS absent mode EEE support is disabled by default in NVRAM.
	  						  						  
-----------------------------
Version 1.07 - April 15, 2011   
-----------------------------

   Enhancement:
   ============
   1. CQ 54515: Disable EEE by default in Boot Code. Set the default state of
      the EEE_Enable bit in NVRAM to disable.
	  
-----------------------------
Version 1.06 - March 30, 2011   
-----------------------------

   Fixes:
   ======
   1. Problem: 
      Both RxCPU will be halted when 0x362c[29:25] is non-zero. 
	  
      Cause: 
      There is a bug in the logic of the function_mode setting up subroutine
      in Bootcode which will halt the RxCPU when 0x362c[29:25] is non-zero. 
      
      Change:
      Fixed the logic in question. Bootcode will only halt the RxCPU according
      to the setting in reg 0x362c[29:25]. 
	  						  
-----------------------------
Version 1.05 - March 30, 2011   
-----------------------------

   Fixes:
   ======
   1. Problem: CQ54066
      Need multiple Magic packets to wake system from S3/S4/S5 in Fiber mode.

      Cause: 
      The wire clock is much faster than the TLP clock in Fiber mode. As a
      result, it fails to capture the WOL event.

      Change:
      Workaround for this would be to derive TLP clock from NCSI PLL by
      setting x3638 bit[26] to 1 when system is running on VAUX and Fiber
      OOB_WOL is enabled. Then switch to PCie Serdes source during normal 
      operation by clearing x3638 bit[26].  
	  
-----------------------------
Version 1.04 - March 28, 2011   
-----------------------------

   Enhancement:
   ============
   1. Adding Single Bit ECC Error Correction support.
      Defined Bit 2 of Extended Configuration in NVRAM to control 
      whether the chip will generate GRC reset upon detection of ECC error.  

-----------------------------
Version 1.03 - March 14, 2011   
-----------------------------

   Fixes:
   ======
   1. Problem: CQ53438
      Flash Controller locks up after exiting SW IDDQ Mode.

      Cause: 
      This failure occurs because upon resuming from S3, S4, or S5, the
      de-assertion of the PERST_L will clear the SW IDDQ bit (0x3638[4]). The
      high to low transition of the SW IDDQ Mode will cause the chip to
      generate a NON_POR Hard_Reset.  The RxCPU Reset is released sooner than
      the release of the reset to the Flash Controller Block.  This causes the
      CPU Romloader code to start accessing the Flash Controller Registers
      while the Flash Controller is held is reset. Under this condition, the
      Flash Controller will not service the request from the Romloader and
      locks up any future Flash Controller Register Access from the HOST or
      APE Firmware.
      
      Change:
      Bootcode will IDDQ the GPHY Digital and GPHY Bias to replace setting the
      SW IDDQ bit.
	  
   2. Problem: CQ53552
      Traffic broken when run chariot TX with jumbo9000 with 5720A0.
	  
      Change:
      Enable FIFO_Available Mode to work around the issue.  
	  
--------------------------------
Version 1.02 - February 25, 2011   
--------------------------------
	  
   Enhancement:
   ============
   1. CQ 53107 - Force Expansion ROM Advertisement Configuration.
      Defined Extended Configuration for each port started at NVRAM offset
      0x278. BIT_1 of Extended Configuration is defined as Force Expansion 
      ROM Advertisement Enable. BC will enable/disable Expansion ROM
      Advertisement based on the state of the Force Expansion ROM
      Advertisement Enable bit after reset. Bootcode will copy Extended
      Configuration to RxCPU Shared Memory offset 0xdf8 and APE RxCPU Shared
      Memory.
	  
   2. Reducing the link status polling frequency to every 1s when EEE is
      enabled.
   
--------------------------------
Version 1.01 - February 16, 2011   
--------------------------------

   Fixes:
   ======
   1. Problem: CQ53110
      PXE Failure to load after issuing CTL_ALT_DEL after invoking B57diag.

      Cause: 
      The MAC clock speed can be slow after issuing CTL_ALT_DEL such that it 
      will take longer for the Bootcode to load.  That in turn cause the PXE
      fails to load on time.
      
      Change:
      Modify BC to force MAC clock speed to 62.5MHz in Vmain mode to provide
      a faster fw loading speed.  The work around will be undone by driver.
      Bootcode will also undo the workaround when entering Vaux mode to
      provide power saving.
	  
--------------------------------
Version 1.00 - February 15, 2011   
--------------------------------

   Fixes:
   ======
   1. Problem: 
      Bootcode enabled LPI with non-EEE link partner.

      Cause: 
      There is an issue in the original EEE enable script. One of the checking
      conditions in this EEE enable script will fall through even with link
      partner is not supporting EEE. As a result the BC will enable LPI even
      with non-EEE link partners.
      
      Change:
      Modify the EEE enable logic in the script to resolve the issue.	

   Enhancements:
   =============
   1. CQ: 52837. Make CL37 a configurable option in NVRAM. Defined Extended
      Configuration for each port started at NVRAM offset 0x278.  BIT_0 of
      Extended Configuration is defined as CL37_EN to control CL37 support.
      Bootcode will set/clear miireg 0x0[12] based on the state of CL37_EN
      after resetting the Fiber port.BC will copy Extended Configuration to
      RxCPU Shared Memory offset 0xdf8 and APE RxCPU Shared Memory.
      
-------------------------------
Version 0.11 - January 06, 2011   
-------------------------------

   Fixes:
   ======
   1. Problem: CQ52007
      New EEE configuration in NVRAM for BC for Cotopaxi

      Change:
      Using Bit 13 of HW_CONFIG instead of Bit 27 of Feature_Config to
      enable/disable EEE. B57diag V14.23 or later will support this change. 
	  
   2. Problem: 
      Bootcode will program port 0 with port 1 SDID.

      Cause:
      In Dual SDID per port support, there is a bug in the SDID select logic
      in Bootcode.
	  
      Change:
      Fixed the logic in question to resolve the issue.
	  
   Enhancements:
   =============
   1. Copy HW_CONFIG to APE shared memory.
   
   2. Enabled and moved up the Gen1/Gen2 selection logic to give Bootcode more
      time to program the selection.
   
---------------------------------
 Version 0.10 - December 16, 2010 
---------------------------------
   Enhancement:
   ============
   1. Removing NVRAM control bit to select Gen1/Gen2.
   
---------------------------------
 Version 0.09 - December 16, 2010 
---------------------------------
   Enhancement:
   ============
   1. Bootcode will not configure bit 15 and bit 20 of reg 0x4910.  Both bits
      will remain in their default state.
	  
---------------------------------
 Version 0.08 - December 15, 2010 
---------------------------------
   Enhancement:
   ============
   1. Adding NVRAM control bit to select Gen1/Gen2.
	  
   2. Adding Dual SDID per port support.  Dual SDID per port will be stored
      in NVRAM starting from 0x22C.
	  
   3. BC will drive GPIO2 to low to avoid power glitch during Vaux to Vmain
      transition.

   4. BC will copy feature_config from RxCPU shared memory to APE shared
      memory after reset.
	  
   5. Enabled APE Heartbeat Monitoring function to monitor the heartbeat of
      APE in Vaux mode as well.
      						  
--------------------------------
 Version 0.07 - December 2, 2010 
--------------------------------
   Enhancement:
   ============
   1. Adding NVRAM control bit to control enabling and disabling EEE support
      in OS absent mode. The default setting is enable.
	  
   2. Updating the Virtual Mac Support. Bootcode will use the Virtual Mac
      Address if Virtual Mac is enabled. Otherwise, Mac Address will be taken
      from NVRAM.
	  
   3. Adding NVRAM control bit to control PCIe Tx De-Emphasis Configuration.  
	  
   4. Adding NVRAM control bit to control enabling and disabling of NCSI Clock
      Output Disable.
  
	  
---------------------------------
 Version 0.06 - November 15, 2010 
---------------------------------

   Enhancement:
   ============
   1. For the FPGA Configuration, read modify write to register 4910 and set
      bit 15 to 1 to enable the fix of the DMA Read Underrun due to the core
      clk running at or faster speed than the TL Clock.
	  
---------------------------------
 Version 0.05 - November 12, 2010 
---------------------------------

   Fixes:
   ======
   1. Problem: 
      Bootcode locked up the MII Mutex.
	  
      Cause:
      Bootcode did not release MII Mutex during EEE setup.

      Change:
      Bootcode will release MII Mutex after accessing MII Reg.                 

   2. Problem: 
      OOB_WOL does not work.
	  
      Cause:
      Bootcode failed to setup OOB_WOL.

      Change:
      Fixed the related logic to enable OOB_WOL.	  
---------------------------------
 Version 0.04g - November 1, 2010 
---------------------------------

   Enhancement:
   ============
   1. Adding EEE support in OS absent mode.

   2. Using mii register 0x00 bit 11 to power down the Serdes port instead of
      Reg 0x3638 bit 15. Reg 0x3638 bit 15 will power down all Serdes ports.  

   3. Using mii register 0x00 bit 11 to power down the GPHY port instead of
      Reg 0x3638 bit 0.  Reg 0x3638 bit 0 will power down all GPHY ports. 

---------------------------------
 Version 0.03g - October 22, 2010 
---------------------------------

   Enhancements:
   =============
   1. Modifying the code such that bootcode will not hang when running with
      APE absent images.

---------------------------------
 Version 0.02g - October 20, 2010 
---------------------------------
   Enhancements:
   =============
   1. Removing unneeded workarounds.

   2. Adding APE support. 

   3. Updating Play Dead Mode/Function Mode.

   4. Updating NVRAM pin strap table. 

   5. Using Reg 0x3630[31:30] to bypass mutex checking for FPGA build.

   6. Before IDDQ the device, BC will check for the WOL enable status of
      both ports.

-----------------------------------
 Version 0.01g - September 30, 2010 
-----------------------------------
   1. Initial engineering release

      This release is for 5720 emulation. It is based on 5719 V0.08g.





